1. Field of the Invention
The present invention is related to integrated circuits incorporating digital circuits, such as logic, memory and latch blocks, and more specifically to techniques for dynamically boosting the voltage of a virtual power supply rail prior to and during an evaluation time of a digital circuit block.
2. Description of Related Art
Static and Dynamic digital circuits are used in memories and logic devices to provide high frequency operation with a minimum of die area for performing logical operations and providing storage functionality. Both synchronous static and dynamic digital circuits have controlled evaluation times in that the operation of the circuit before and during a time at which an output value of the digital circuit block evaluates or changes state, i.e., is determined from the input logic, latch input or storage cell value is used advantageously to reduce circuit complexity and/or power consumption.
Groups of digital circuits, which are sometimes referred to as “macros”, have been power-managed in existing circuits to reduce power consumption, except during certain intervals of time in which power supply current is drawn to provide a read or write of a storage cell value, or the determination of a logic combination. For example, a dynamic logic circuit may draw no current, or have very low leakage current levels, except when a signal node is pre-charged with a voltage and then selectively discharged to produce the combinatorial output or storage cell value. A static logic circuit or storage cell only draws significant current when a state change occurs.
Digital circuits have been implemented that include virtual power supply nodes that can be disabled or set to a reduced voltage when the logic circuits are not evaluating, or multiple power supplies can be used to supply higher voltages to critical circuits. In some implementations, circuits have been provided that boost the power supply voltage supplied to the digital circuits during their evaluation phase to reduce the static power supply voltage by including a boost transistor. Such boosting reduces overall power supply voltage requirements. However, the energy expended in changing the voltage of the virtual power supply node voltage offsets any advantage gained, since the virtual power supply nodes typically have large shunt capacitance, i.e., capacitance between the virtual power supply node and the corresponding power supply return, due to the large numbers of devices that are connected to the virtual power supply nodes.
It would therefore be desirable to provide a virtual power supply circuit for synchronous digital circuits, and other circuits having a predictable evaluate time, that provides for reduction in overall power supply voltage and energy consumption.